This invention relates to a computer system, and more particularly, to a dual bus system in a computer system for providing separate paths, the first path for instruction fetch and operand read/write and a second path for the peripheral I/O, thereby achieving a degree of simultaneity increasing memory bandwidth and obtaining higher system performance.
In earlier systems, a single bus for all instruction fetches, operand read/writes, and peripheral I/O was utilized. The single bus allowed for no degree of simultaneity and therefore only a single memory cycle at a time could be serviced, i.e. instruction fetches, operand read/writes, and peripheral I/O. The simultaneity is achieved in the dual bus system of the present application by providing separate paths for instruction fetch and operand read/write from the path utilized for the peripheral I/O. Therefore, the peripheral I/O can be made to overlap/interleave with the instruction fetch, and to a lesser extent the operand read/write can be made to partially overlap with the peripheral I/O.